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Ms. Pathak specializes in all aspects of semiconductor devices and related systems issues. She has 35 years of professional experience—3 years in teaching and rest in the semiconductor industry. Ms. Pathak has strong background in new technology and product development including circuit and logic design, product testing, manufacturing, yield enhancement, and failure analysis. Ms. Pathak has managed teams that have defined new technologies and designed and manufactured semiconductor products using these state of the art technologies. These products are used in computers and peripherals, cameras, cell phones, automobiles, telecommunications, electronic security, space and military electronics, and many other consumer applications. Some of these products have included: ROMs, SRAMs, EPROMs, FLASH, EEPROMs, PLDs, FPGA’s, Configurators, Video Display chips, Smart Cards, FPSLIC, and various other logic chips. She has worked on technologies ranging from 5 microns down to 0.13 microns and from simple NMOS process to complex FLASH and TFT( thin film transistors) processes. Ms. Pathak has built and managed professional teams who have successfully defined and manufactured new products and technologies. Her teams have consisted of offsite engineers in Europe and several locations in United States, and were responsible for all aspects of the semiconductor business including, product definition, marketing, software development, applications and customer support, product and technology design, testing, product engineering, failure analysis, and manufacturing. Ms. Pathak’s experience also includes negotiations with foundries and successfully bringing up a new technologies and product line in offshore foundries and design houses.
Pathak S. A 13ns Mb CMOS EPROM using 1-T FAMOS technology. ISSCC Digest of Technical Papers, pp. 42–43, February 1993. Pathak S. A 25ns 16k CMOS PROM using 4-transistor cell. IEEE International solid States Circuits Conference, February 14, 1985. Pathak S. A 25ns 16k CMOS PROM and differential design techniques. IEEE Journal of Solid State Circuits, October 1985. Pathak S. A 64k electrically erasable and programmable read only memory. IEEE International solid State Circuits Conference, February 1978.
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- M.E., Control Systems, SGS Institute of Technology and Science, India, 1972
- B.E., Electrical Engineering, SGS Institute of Technology and Science, India, 1969
Patent 6618289: High voltage bit/column latch for low vdd operation, September 9, 2003.
Patent 6,476,785: Drive circuit for liquid crystal display cell, September 9, 2003.
Patent 6,411,549: Reference cell for high speed sensing in non-volatile memories, November 5, 2002.
Patent 6,320,454: Low power voltage regulator circuit for use in an integrated circuit device, June 25, 2002.
Patent 6,141,257: Device for the configuration of options in an integrated circuit and implementation method, November 20, 2001.
Patent 6,140,993: Circuit for transferring high voltage video signal without signal loss, October 31, 2000.
Patent 6,115,305: Method and apparatus for testing a video display chip, October 31, 2000.
Patent 5,999,038: Fuse circuit having zero power draw for partially blown condition, September 5, 2000.
Patent 5,963,496: Sense amplifier with zero power idle mode, October 5, 1999.
Patent 5,946,267: Zero power high speed configuration memory, August 31, 1999.
Patent 5,936,444: Zero power power-on reset circuit, August 10, 1999.
Patent 5,917,754: Semiconductor memory having a current balancing circuit, June 29, 1999.
Patent 5,781,469: Bitline load and precharge structure for an SRAM memory, July 14, 1998.
Patent 5,731,734: Zero power fuse circuit, March 24, 1998.
Patent 5,680,346: High-speed non-volatile electrically programmable and erasable cell and method, October 21, 1997.
Patent 5,493,244, Breakdown protection circuit using high voltage detection, February 20, 1996.
Patent 5,473,500: Electrostatic discharge circuit for high speed, high voltage circuitry, December 5 1995.
Patent 5,440,508: Zero power high speed programmable circuit devise architecture, August 8, 1995.
Patent 5,383,193: Method for testing non-volatile memories, January 17, 1995.
Patent 5,272,674: High speed memory sense amplifier with noise reduction, December 21, 1993.
Patent 5,027,320: EPROM circuit having enhanced programmability and improved speed and reliability, June 25, 1991.
Patent 4,978,905: Noise reduction output buffer, December 18, 1991.
Patent 4,364,828: MOS Static decoding circuit, April 28, 1981.
Patent 4,223,394: Sensing amplifier for floating gate memory devices, September 16, 1980.
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