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Mr. Lange's areas of expertise include electrical and microelectronic systems, particularly as they relate to circuit design and microprocessors . He also specializes in failure analysis of such systems and consults on matters of intellectual property. Mr. de Lange has extensive experience with static and dynamic custom CMOS integrated circuit design for microprocessors. Additionally he was team lead for design, verification, and yield optimization of telecom and consumer electronic integrated circuits during development and first year of manufacturing. He has implemented resistance and capacitance test structures for technology modeling, and has been in charge of the package design for a microprocessor component. Prior to joining Exponent, Mr. de Lange worked at Sun Microsystems in various teams covering eight subsequent microprocessor projects, including general purpose and media microprocessors. This work included logic verification and debuging, physical implementation and verification of large custom designs, register files, dynamic comparators, adders, shifters and standard cell libraries work. Prior to this, he was employed at Intergraph Corp, where he worked on three generations of Clipper microprocessors implementing register files, I/O cells and technology test structures for resistance, capacitance, and device parameter extraction. He initiated implementation of extraction models for interconnect layers used by Computer Aided Design programs to allow the designers to perform accurate timing modeling. Prior to his tenure at Intergraph, Mr. de Lange worked on assignment from Siemens, Munich, Germany at Intel in Oregon, U.S., contributing to three microprocessor components. He was responsible for design and implementation of PLAs, ROMs, RAMs, CAMs, queues, clock circuits, register files, bus transceivers and I/O circuits. He also performed the ball grid array package design of one of the microprocessor components.

Lev LA, Charnas A, Tremblay M, Dalal AR, Frederick BA, Srivatsa CR, Greenhill D, Wendell DL, Anderson DDP, Hingarh E, Razzack HI, Kaku I, Shin JM, Levitt K, Allen ME, Ferolito M, Bartolotti PA, Yu RI, Melanson RK, Shah RJ, Nguyen SI, Mitra S, Reddy SS, Ganesan V, de Lange WJ. A 64-b microprocessor with multimedia support. IEEE Journal of Solid State Circuits, November 1995. Kowalczyk A, Adler V, Amir C, Chiu F, Choon PC, De Lange WJ, Yuefei GG, Canh ST, Hoang BHK, Kao S. Cong YS, Kumar K, Liebermensch SLL, Malur AXL, Martin NG, Ngo AA, Orginos H, Shih I, Sur L, Tremblay B, Tzeng M, Vo A, Zambare D, Zong SJ. The first MAJC microprocessor: a dual CPU system-on-a-chip. IEEE Journal of Solid State Circuits, November 2001. de Lange W. Accurate determination of CMOS capacitance parameters using multilayer structures. IEEE, International Conference on Microelectronic Test Structures, San Diego, 1992. de Lange W. High performance RISC microprocessor design. Tutorial, presented at the VIIth Congress of the Brazilian Microelectronics Society at Sao Paulo, Brazil, 1992. Hart F, de Lange W. Development, design, and implementation of the C400 Microprocessor. Invited paper presented at the University of Sao Paulo and at the Federal University of Rio de Janeiro, Brazil, 1992. Kowalczyk A, Adler V, Amir C, Chiu F, Choon PC, De Lange WJ, Yuefei GG, Canh ST, Hoang BHK, Kao S, Cong Khieu Kumar YS, Liebermensch SLL, Malur AXL, Martin NG, Ngo AA, Sung-Hun Oh Orginos H, Shih I, Sur L, Tremblay B, Tzeng M, Vo A, Zambare D, Jin Zong S. First generation MAJC dual microprocessor. IEEE ISSCC, 2001.

- Senior Circuit Design Engineer; Team Manager, Sun Microsystems, 1993–2007
- Senior System Consultant; Project Manager, Intergraph Corp., 1987–1993
- Senior Circuit Design Engineer assigned by Siemens Corp, Intel Corp., 1983–1987
- Team Manager; Project Manager; Circuit Design Engineer, Siemens Corp., Germany, 1973–1987
- Lieutenant of Technical Staff, Royal Dutch Army at headquarters of Technical Staff, The Hague, The Netherlands, 1971–1972
- Scientist, Philips’s Research Laboratories, Eindhoven, The Netherlands, 1970–1971
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- M.S., Electrical Engineering, University of Twente, Enschede, 1971
- B.S., Electrical Engineering and Business Administration, University of Twente, Enschede, 1968

Patent 5,754,569: Apparatus and Method for Comparing and Validating Digital Words, May 19, 1998.
Patent 5,862,085: Apparatus and Method for Differential Comparison of Digital Words, January 19, 1999.
Patent 6,091,259: Apparatus for Accelerating Digital Signal Transitions using Acceleration and Termination Circuits, July 18, 2000.
Patent 6,091,261: Apparatus and Method for Programmable Delays using Boundary Scan Chain, July 18, 2000.
Patent 7,145,810: High Density Memory and Multiplexer Control Circuit for Use Therein, December 5, 2006.
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