US Patent 6,922,138: Vehicle Specific Messaging Apparatus and Method, July, 2005.
US Patent 6,981,110: Hardware Enforced Virtual Sequentiality, December, 2005.
U.S. Patent 7,035,998: Clustering Stream and/or Instruction Queues for Multi-Streaming Processors, April, 2006 (M. Nemirovsky, N. Sampath, E. Musoll, H. Urdaneta).
US Patent 7,042,887: Method and Apparatus for Non-Speculative Pre-Fetch Operations in Data Packet Processing, May, 2006 (N. Sampath, E. Musoll, M. Nemirovsky).
US Patent 7,058,064: Queueing System for Processors in Packet Routing Operations, June, 2006 (M. Nemirovsky, E. Musoll, N. Sankar, N. Sampath, A. Nemirovsky).
US Patent 7,065,096: Method for Allocating Memory Space for Limited Packet Head and/or Tail Growth, June, 2006 (E. Musoll, M. Nemirovsky).
US Patent 7,107,402: Packet Processor Memory Interface, September, 2006.
US Patent 7,139,901: Extended Instruction Set for Packet Processing Applications, November, 2006 (E. Musoll, M. Nemirovsky).
US Patent 7,155,516: Method and Apparatus for Overflowing Data Packets to a Software-Controlled Memory When They Do Not Fit Into a Hardware-Controlled Memory, December, 2006 (E. Musoll, M. Nemirovsky).
US Patent 7,165,257: Context Selection and Activation Mechanism for Activating One of a Group of Inactive Contexts in a Processor Core for Servicing Interrupts, January, 2007 (E. Musoll, M. Nemirovsky).
US Patent 7,197,043: Method for Allocating Memory Space for Limited Packet Head and/or Tail Growth, March, 2007 (E. Musoll, M. Nemirovsky).
US Patent 7,257,814: Method and Apparatus for Implementing Atomicity of Memory Operations in Dynamic Multi-Streaming Processors, August, 2007 (M. Nemirovsky).
US Patent 7,280,548: Method and Apparatus for Non-speculative Pre-fetch Operation in Data Packet Processing, October, 2007 (N. Sampath, E. Musoll, M. Nemirovsky).
US Patent 7,319,379: Profile-Based Messaging Apparatus and Method, January, 2008.
US Patent 7,346,710: Apparatus for Input/Output Expansion Without Additional Control Line Wherein First and Second Signals Transition Directly to a Different State When Necessary to Perform Input/Output, March, 2008.
US Patent 7,360,217: Multi-Threaded Packet Processing Engine for Stateful Packet Processing, April, 2008 (M. Nemirovsky, E. Musoll, J. Huynh).
US Patent 7,441,088: Packet Processor Memory Conflict Prediction, October, 2008.
US Patent 7,444,481: Packet Processor Memory Interface With Memory Conflict Value Checking, October, 2008.
US Patent 7,475,200: Packet Processor Memory Interface With Write Dependency List, January, 2009.
US Patent 7,475,201: Packet Processor Memory Interface With Conditional Delayed Restart, January, 2009.
US Patent 7,478,209: Packet Processor Memory Interface With Conflict Detection And Checkpoint Repair, January, 2009.
US Patent 7,482,910: Apparatus, System, and Computer Program Product for Presenting Unsolicited Information to a Vehicle or Individual, January, 2009.
US Patent 7,487,304: Packet Processor Memory Interface With Active Packet List, February, 2009.
US Patent 7,496,721: Packet Processor Memory Interface With Late Order Binding, February, 2009.
US Patent 7,506,104: Packet Processor Memory Interface With Speculative Memory Reads, March, 2009.
US Patent 7,529,907: Method and Apparatus for Improved Computer Load and Store Operations, May, 2009 (M. Nemirovsky, E. Musoll, N. Sankar).
US Patent 7,551,626: Queueing System for Processors in Packet Routing Operations, June, 2009 (M. Nemirovsky, E. Musoll, N. Sankar, N. Sampath, A. Nemirovsky).
US Patent 7,606,942: Method for Input Output Expansion in an Embedded System Utilizing Controlled Transitions of First and Second Signals, October, 2009.
US Patent 7,650,605: Method And Apparatus For Implementing Atomicity Of Memory Operations In Dynamic Multi-streaming Processors, January, 2010 (M. Nemirovsky).
US Patent 7,668,954: Unique Identifier Validation, February, 2010.
US Patent 7,715,410: Queueing System for Processors in Packet Routing Operations, May, 2010 (M. Nemirovsky, E. Musoll, N. Sankar, N. Sampath, A. Nemirovsky).
US Patent 7,739,452: Method and Apparatus for Hardware Enforced Virtual Sequentiality, June, 2010.
US Patent 7,765,554: Context Selection and Activation Mechanism for Activating One of a Group of Inactive Contexts in a Processor Core for Servicing Interrupts, July, 2010 (E. Musoll, M. Nemirovsky).
US Patent 7,876,427: Headlamp Alignment Detection Using A Network Of Independent Sensor Units, January, 2011.
US Patent 7,877,481: Method And Apparatus For Overflowing Data Packets To A Software-Controlled Memory When They Do Not Fit Into A Hardware-Controlled Memory, January, 2011 (E. Musoll, M. Nemirovsky).
US Patent 8,004,663: Headlamp Aim Detection With Sensors Independent From Host Control Unit, August, 2011.
US Patent 8,131,882: Method for Input Output Expansion in an Embedded System Utilizing Controlled Transitions of First and Second Signals, March, 2012.
US Patent 8,184,275: Vehicle Headlamp Monitoring Using A Network Accessible User Interface, May, 2012.
US Patent 8,214,482: Remote Log Repository With Access Policy, July, 2012.
US Patent 8,275,996: Incremental Encryption Of Stored Information, September, 2012.
US Patent 8,301,753: Endpoint Activity Logging, October, 2012.
US Patent 8,307,072: Network Adapter Validation, November, 2012.
US Patent 8,429,420: Time-Based Key Management For Encrypted Information, April, 2013.
US Patent 8,732,482: Incremental Encryption Of Stored Information, May, 2014.
US Patent 8,806,066: Method for Input Output Expansion in an Embedded System Utilizing Controlled Transitions of First and Second Signals, August, 2014.
US Patent 8,812,875: Virtual Self-Destruction Of Stored Information, August, 2014.
US Patent 8,917,190: Method of Restricting Turns at Vehicle Intersections, December, 2014.
US Patent 9,245,155: Virtual Self-Destruction of Stored Information, January, 2016.
US Patent 10,051,555: User Specific Access Throttler For Access Points, August, 2018.