Po Yen Chien
Po-Yen Chien, Ph.D.
Senior Associate
Electrical Engineering & Computer Science
Menlo Park

Dr. Chien specializes in semiconductor device physics and integrated circuit manufacturing technology. He has extensive experience in technology computer aided design (TCAD) simulation, fabrication, electrical/material characterization and optimization of MOSFET devices in the nanoscale regime for digital and/or analog applications. His expertise also extends to component-level failure analysis from circuit/design, device/process/fab, and testing perspectives.

Prior to joining Exponent, Dr. Chien worked at Maxim Integrated where he focused on yield enhancement and quality activities for audio and real-time-clock chips. While there, he applied data and reliability analysis techniques as part of an international cross-functional team to determine the root cause of chip failures, and drive the team to deliver reliable fixes. Before that, he worked at Taiwan Semiconductor Manufacturing Company to help introduce in-line nondestructive inspection tools for high-k dielectrics and worked at AU Optronics as a design engineer to develop TFT-LCD panels for hand-held devices. He was also a lecturer in electromagnetics at San Francisco State University.

During his Ph.D. work at University of California Los Angeles, Dr. Chien simulated nanoscale bulk MOSFETs with deeply retrograde channel doping profiles using TCAD tools and predicted their limitations compared to SOI and FinFET for digital/analog applications. He fabricated, characterized, and optimized CVD-growth WSe2 FET and achieved state-of-the-art hole mobility. He also worked on prototyping CdTe-based X-ray detector technology for dental applications. He mastered cleanroom equipment skills such as lithography, etching, PVD, ALD, and thermal processes as well as electrical and material characterization techniques like C-V, I-V, SEM, and Ramen spectroscopy. His skill set also includes failure analysis using Dual-Beam FIB, OBIRCH, and Emission microscopy (EMMI).

CREDENTIALS & PROFESSIONAL HONORS

  • Ph.D., Electrical Engineering, University of California, Los Angeles (UCLA), 2016
  • M.S., Engineering and System Science, National Tsing Hua University, Taiwan, 2007
  • B.S., Electrical Engineering, National Central University, Taiwan, 2005
  • Outstanding Interview Scholarship, 2005

LANGUAGES

  • Mandarin

Publications

Zhang M, Chien PY, Woo J, Comparative Simulation Study on MoS2 FET and CMOS transistor. TENCON, 2015.

Woo J, Chien PY, Yang F, Song SC, Chidambaram Chidi, Wang Joseph, Yeap Geoffrey, Improved Device Variability in Scaled MOSFETs with deeply retrograde channel profile. Microelectronics Reliability, vol. 54, Issue 6-7, pp. 1090-1095, 2014.

Chang HY, Adams B, Chien PY, Li J, Woo J, Improved Subthreshold and Output Characteristics of Source-Pocket Si Tunnel FET by the Application of Laser Annealing. IEEE Trans. on Electron Device, vol. 60, No. 1, pp. 92-96, 2013.

Fu CH, Chien PY, Chang-Liao KS, Wang TK, Wu WF, Characteristics and Thermal Stability of MOS Devices with MoN/TiN and TiN/MoN Metal Gate Stacks. Solid State Electronics, vol. 52, Issue 10, pp. 1512-1517, 2008.

Presentations

Chien PY, Zhang M, Huang SC, Lee MH, Hsu HR, Ho YT, Chu YC, Jong CA, Woo J, Reliable Doping Technique for WSe2 by W:Ta Co-Sputtering Process. Poster Presentation, IEEE Silicon Nanoelectronics Workshop, Honolulu, HI, 2016.

Prior Experience

Member of Technical Staff, Maxim Integrated, 2016-2018

Lecturer, San Francisco State University, 2017

Teaching and Research Assistant, University of California, Los Angeles, 2011-2016

Intern, Taiwan Semiconductor Manufacturing Company, 2011

Array Cell Design Engineer, AU Optronics, 2008-2009

Engineer Assistant, Taiwan Semiconductor Manufacturing Company, 2007

Research Assistant, National Tsing-Hua University, 2005-2007

Professional Affiliations

Institute of Electrical and Electronics Engineers – Member

IEEE Electron Device Society – Member

Additional Information

Peer Reviewer

IEEE Transaction on Electron Devices

CREDENTIALS & PROFESSIONAL HONORS

  • Ph.D., Electrical Engineering, University of California, Los Angeles (UCLA), 2016
  • M.S., Engineering and System Science, National Tsing Hua University, Taiwan, 2007
  • B.S., Electrical Engineering, National Central University, Taiwan, 2005
  • Outstanding Interview Scholarship, 2005

LANGUAGES

  • Mandarin