Dr. Souri’s background is in electrical and electronic engineering and computer systems. His professional activities include addressing issues related to electrical components, semiconductors, integrated circuits (ICs), electronics and software. His specialties include intellectual property analysis, manufacturing, reliability and failure analysis of electronic products and assemblies, medical devices, optical systems, computer memories, circuit protection, automotive electronics, computer communications, networks, and software.
Dr. Souri received his Ph.D. in Electrical Engineering at Stanford University on 3-Dimensional integration of ICs and has taught several courses on IC fabrication, optical fiber communications, TCP/IP networking, and communications protocols and implementation of systems on 3-D chips. He also read Engineering Science at Balliol College, Oxford, where he specialized in photoreflectance microscopy of semiconductor materials. His research interests include: solid state light emitting devices; semiconductor materials, devices and fabrication processes; microprocessor architecture and circuit design; audio/video/image processing software and content delivery technologies; medical devices including resectoscopes, cochlear implants and ICDs; embedded controls systems for computer hard disk drives; IC packaging and printed circuit board assembly; display technologies; telephony, mobile communications, and networking.
- Ph.D., Electrical Engineering, Stanford University, 2003
- M.S., Electrical Engineering, Stanford University, 1994
- M.A., University of Oxford, UK, 2007
- B.A., Engineering Science, University of Oxford, UK (honors), 1992
Patent 6,188,556: Two-Terminal Transistor PTC Circuit Protection Devices, WO0024126, 2001 (with C. McCoy, H. Duffy, A. Cogan, and R. Bommakant).
Patent 6,181,541: Transistor-PTC Circuit Protection Devices, WO0024105, 2001 (with H. Duffy, A. Cogan, M. Munch, and N. Nickols).
Patent 6,153,948: Electronic Circuits with Wide Dynamic Range of On/Off Delay Time, WO001249, 2000 (with A. Cogan).
Patent 5,569,495: Method of Making Varistor Chip with Etching to Remove Damaged Surfaces, CA2220931, EP0826225, WO963978, JP11505375T, 1996 (with A. Evans, T. Tsukada, and R. Dupon).